Jeffrey S. Vetter, Ph.D., is a Distinguished R&D Staff Member, and the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division of Oak Ridge National Laboratory. Vetter also holds a joint appointment at the Electrical Engineering and Computer Science Department of the University of Tennessee-Knoxville. From 2005 through 2015, Vetter held a Joint position at Georgia Institute of Technology, where, from 2009 to 2015, he was the Principal Investigator of the NSF Track 2D Experimental Computing XSEDE Facility, named Keeneland, for large scale heterogeneous computing using graphics processors, and the Director of the NVIDIA CUDA Center of Excellence.
Vetter earned his Ph.D. in Computer Science from the Georgia Institute of Technology. He joined ORNL in 2003, after stints as a computer scientist and project leader at Lawrence Livermore National Laboratory, and postdoctoral researcher at the University of Illinois at Urbana-Champaign. The coherent thread through his research is developing rich architectures and software systems that solve important, real-world high performance computing problems. In particular, he has been investigating the effectiveness of next-generation architectures, such as graphics processors, massively multithreaded processors, non-volatile memory systems, heterogeneous multicore processors, and field-programmable gate arrays (FPGAs), for key applications. His recent books, entitled “Contemporary High Performance Computing: From Petascale toward Exascale (Vols. 1 and 2),” survey the international landscape of HPC.
Vetter is a Fellow of the IEEE, and a Distinguished Scientist Member of the ACM. Vetter, as part of an interdisciplinary team from Georgia Tech, NYU, and ORNL, was awarded the Gordon Bell Prize in 2010. Also, his work has won awards at major conferences: Best Paper Awards at the International Parallel and Distributed Processing Symposium (IPDPS) and EuroPar, Best Student Paper Finalist at SC14, and Best Presentation at EASC 2015. In 2015, Vetter served as the Technical Program Chair of SC15 .
Keynote: Exploring Emerging Memory Technologies in Extreme Scale High Performance Computing
Concerns about energy-efficiency and cost are forcing our community to reexamine system architectures, and, specifically, the memory and storage hierarchy. While memory and storage technologies have remained relatively stable for nearly two decades, new architectural features, such as deep memory hierarchies, non-volatile memory (NVM), and near-memory processing, have emerged as possible solutions. However, these architectural changes will have a major impact on software systems and applications in our HPC ecosystem. Software will need to be redesigned to exploit these new capabilities. In this talk, I will sample these emerging memory technologies, discuss their architectural and software implications, and describe several new approaches to programming these systems. One system is Papyrus (Parallel Aggregate Persistent -yru- Storage); it is a programming system that aggregates NVM from across the system for use as application data structures, such as vectors and key-value stores, while providing performance portability across emerging NVM hierarchies.